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 STP40NF03L
N-channel 30V - 0.018 - 40A - TO-220 STripFETTM Power MOSFET
General features
Type STP40NF03L
VDSS 30V
RDS(on) <0.022
ID 40A
Low threshold device
3 1 2
Description
This Power MOSFET is the latest development of STMicroelectronics unique "Single Feature SizeTM" strip-based process. The resulting transistor shows extremely high packing density for low on-resistance, rugged avalanche characteristics and less critical alignment steps therefore a remarkable manufacturing reproducibility.
TO-220
Internal schematic diagram
Applications
Switching application
Order codes
Part number STP40NF03L Marking P40NF03L Package TO-220 Packaging Tube
February 2007
Rev 4
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www.st.com 12
Contents
STP40NF03L
Contents
1 2 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 Electrical characteristics (curves) ............................. 6
3 4 5
Test circuit
................................................ 8
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
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STP40NF03L
Electrical ratings
1
Electrical ratings
Table 1.
Symbol VDS VGS ID ID IDM
(1)
Absolute maximum ratings
Parameter Drain-source voltage (VGS = 0) Gate- source voltage Drain current (continuous) at TC = 25C Drain current (continuous) at TC = 100C Drain current (pulsed) Total dissipation at TC = 25C Derating Factor Value 30 16 40 28 160 70 0.46 250 -55 to 175 Max. operating junction temperature Unit V V A A A W W/C mJ C
Ptot EAS (2) Tstg Tj
Single pulse avalanche energy Storage temperature
1. Pulse width limited by safe operating area. 2. Starting Tj = 25 C, ID = 20A, VDD = 15V
Table 2.
Rthj-case Rthj-amb TJ
Thermal data
Thermal resistance junction-case max Thermal resistance junction-ambient max Maximum lead temperature for soldering purpose 2.1 62.5 300 C/W C/W C
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Electrical characteristics
STP40NF03L
2
Electrical characteristics
(TCASE=25C unless otherwise specified) Table 3.
Symbol V(BR)DSS
On/off states
Parameter Drain-source breakdown voltage Zero gate voltage drain current (VGS = 0) Gate-body leakage current (VDS = 0) Gate threshold voltage Static drain-source on resistance Test conditions ID = 250A, VGS =0 VDS = max ratings VDS = max ratings, TC = 125C VGS = 16V VDS = VGS, ID = 250A VGS = 10V, ID = 20A VGS = 4.5V, ID = 20A 1 1.7 0.018 0.028 Min. 30 1 10 100 2.5 0.022 0.035 Typ. Max. Unit V A A nA V
IDSS
IGSS VGS(th) RDS(on)
Table 4.
Symbol gfs (1) Ciss Coss Crss td(on) tr td(off) tf Qg Qgs Qgd
Dynamic
Parameter Forward transconductance Input capacitance Output capacitance Reverse transfer capacitance Turn-on delay time Rise time Turn-off delay time Fall time Total gate charge Gate-source charge Gate-drain charge Test conditions VDS = 10V, ID = 20A Min. Typ. 20 770 255 60 14 80 25 16 10.5 4 4.5 15 Max. Unit S pF pF pF ns ns ns ns nC nC nC
VDS = 25V, f = 1MHz, VGS = 0
VDD = 15V, ID = 20A RG = 4.7 VGS = 4.5V (see Figure 13) VDD = 15V, ID = 40A, VGS = 4.5V (see Figure 14)
1. Pulsed: Pulse duration = 300 s, duty cycle 1.5%.
4/12
STP40NF03L
Electrical characteristics
Table 5.
Symbol ISD ISDM (1) VSD (2) trr Qrr IRRM
Source drain diode
Parameter Source-drain current Source-drain current (pulsed) Forward on voltage ISD = 40A, VGS = 0 34.5 30 2 Test conditions Min. Typ. Max. 40 160 1.5 Unit A A V ns nC A
ISD = 40A, Reverse recovery time di/dt = 100A/s, Reverse recovery charge VDD = 15V, Tj = 150C Reverse recovery current (see Figure 15)
1. Pulse width limited by safe operating area. 2. Pulsed: Pulse duration = 300 s, duty cycle 1.5%
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Electrical characteristics
STP40NF03L
2.1
Figure 1.
Electrical characteristics (curves)
Safe operating area Figure 2. Thermal impedance
Figure 3.
Output characteristics
Figure 4.
Transfer characteristics
Figure 5.
Transconductance
Figure 6.
Static drain-source on resistance
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STP40NF03L Figure 7. Gate charge vs. gate-source voltage Figure 8.
Electrical characteristics Capacitance variations
Figure 9.
Normalized gate threshold voltage vs. temperature
Figure 10. Normalized on resistance vs. temperature
Figure 11. Source-drain diode forward characteristics
Figure 12. Normalized BVDSS vs. temperature
7/12
Test circuit
STP40NF03L
3
Test circuit
Figure 14. Gate charge test circuit
Figure 13. Switching times test circuit for resistive load
Figure 15. Test circuit for inductive load Figure 16. Unclamped Inductive load test switching and diode recovery times circuit
Figure 17. Unclamped inductive waveform
Figure 18. Switching time waveform
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STP40NF03L
Package mechanical data
4
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com
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Package mechanical data
STP40NF03L
TO-220 MECHANICAL DATA
DIM. A b b1 c D E e e1 F H1 J1 L L1 L20 L30 mm. MIN. 4.40 0.61 1.15 0.49 15.25 10 2.40 4.95 1.23 6.20 2.40 13 3.50 16.40 28.90 3.75 2.65 3.85 2.95 0.147 0.104 TYP MAX. 4.60 0.88 1.70 0.70 15.75 10.40 2.70 5.15 1.32 6.60 2.72 14 3.93 MIN. 0.173 0.024 0.045 0.019 0.60 0.393 0.094 0.194 0.048 0.244 0.094 0.511 0.137 0.645 1.137 0.151 0.116 inch TYP. MAX. 0.181 0.034 0.066 0.027 0.620 0.409 0.106 0.202 0.052 0.256 0.107 0.551 0.154
oP
Q
10/12
STP40NF03L
Revision history
5
Revision history
Table 6.
Date 09-Sep-2004 21-Jun-2005 16-Aug-2006 21-Feb-2007
Revision history
Revision 1 2 3 4 Preliminary version Complete version with curves New template, no content change Typo mistake on page 1 Changes
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STP40NF03L
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